1. Field of the Invention
The present invention relates to a sequential semiconductor device tester, and in particular to a sequential semiconductor device tester wherein a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.
2. Description of the Related Art
A tester for testing a semiconductor device tests whether the semiconductor device is defective. The tester for testing the semiconductor device is designed and developed according to a development state of a memory device, a DRAM in particular which takes up most of the memory devices since the tester for testing the semiconductor device is mostly used for testing the memory devices.
The development of the DRAM is progressing from an EDO (Extended Data Output) DRAM, SDRAM (Synchronous DRAM), Rambus DRAM to DDR (Double Data Rate) DRAM.
In order to test the DRAM, a high speed and a high accuracy are required for the tester so as to correspond to a high speed DRAM. In addition, as a capacity of the memory is increased, a time required for testing the DRAM also increases. Therefore, a testing speed is also required to be increased. Moreover, a cost for testing the memory should be reduced by embodying a miniaturized and economical tester.
Of the tester for testing the semiconductor device, the memory tester in particular is typically used for testing and verifying a memory component or a memory module in a form of a SIMM or DIMM. The tester detects a functional defect of the memory module or the memory component prior to an installation thereof in a real computer system.
The tester is classified into a hardware semiconductor device tester and a software diagnostic program executed in a PC environment. However, since the software diagnostic program diagnoses a state of the memory when the memory module or the memory component is installed in the real computer, the hardware semiconductor device tester is mainly used during a semiconductor memory manufacturing process.
The tester may be classified as a high-end tester referred to as an ATE (Automatic Test Equipment), a medium range memory tester and a low-end memory tester.
The ATE which is the high-end tester is typically used in order to carry out a test process of the memory device. The conventional ATE carries out tests such as a DC test for testing whether a DC parameter is suitable for a digital operation of a circuit, a transmission delay time of signals, and an AC margin related to a set-up time and a hold time. The ATE also generates a test pattern and a timing for the test. However, a manufacturing cost of the ATE is high since the ATE is manufactured using a dedicated equipment such as a main frame having a large size and a high price.
FIG. 1 is a block diagram illustrating a conventional semiconductor device tester.
As shown in FIG. 1, the conventional tester comprises a pattern generator 110, a timing generator 120, a format controller 130, a driver 140, a comparator 150, and a test result storage 160. In addition to these components, the conventional tester may comprise a power supply controller for the DC test, a component for generating a clock signal, a component for supplying a power for an operation of a DUT (Device Under Test) 180, a component for relaying a test pattern data to the DUT 180 and receiving a test result from the DUT 180, a component for receiving a test pattern program from an outside, and a component for transmitting the test result to the outside. However, a description thereof is omitted.
The pattern generator 110 generates the test pattern data required for testing the DUT 180 based on the test pattern program. For instance, the test pattern program is written to include an instruction for carrying out various operations in order to carry out the test. The pattern generator 110 generates the test pattern data by receiving and interpreting the test pattern program from an external storage for instance. The test pattern data includes a data such as a command, address and a data inputted to the DUT 180. In addition, an expected data corresponding to the generated test pattern data is generated.
The timing generator 120 generates a timing edge which is a reference for converting the test pattern data generated in the pattern generator 110 into various waveforms. The timing edge is generated using a plurality of clocks for a smooth conversion.
The format controller 130 converts the test pattern data to a desired waveform based on the timing edge.
The driver 140 transmits the converted test waveform to the DUT 180.
The comparator 150 tests the DUT 180 by comparing the test output data being outputted from the DUT 180 after an operation of the DUT 180 is complete by the test waveform applied to the DUT 180 with the expected data generated in the pattern generator 110.
The test result storage 160 stores a test result based on a result of the comparison of the comparator 150. For instance, an information on a defective DUT is stored.
As described above, the conventional ATE is very highly priced. Therefore, it is preferable that a manufacturer designs the highly priced ATE efficiently in order to increase a competitiveness by minimizing a manufacturing cost thereof. For the efficient design of the ATE, the generation of the test pattern and the timing should be optimized.
Moreover, since the conventional ATE is very highly priced, a tester for testing the semiconductor device under an actual environment, i.e. an application environment tester may be used instead of the ATE.
For instance, Korean Patent Application No. 10-2002-0004428 filed on Jan. 25, 2002 by Silicontech titled “SEMICONDUCTOR MEMORY TESTER” discloses the application environment tester. In addition, Korean Patent Application No. 10-2004-78152 filed on Oct. 1, 2004 by the Applicant titled “SOCKET INTERFACE FOR APPLICATION TEST OF SEMICONDUCTORDEVICE” wherein the test is carried out using an electronic device such as a hard disk drive, a graphic board and a DVD drive instead of a PC mainboard, and Korean Patent Application No. 10-2004-78153 filed on Oct. 1, 2004 by the Applicant titled “TEST FIXTURE FOR APPLICATION TEST AND SEMICONDUCTORDEVICE APPLICATION TESTER HAVING THEREOF” disclose the application environment tester.
The application environment tester overcomes problems of the ATE that a long time is required for the test and that a detection of a defectiveness is limited under an application environment. Therefore, the application environment tester may carry out the test under the application environment using various diagnostic program such that the application environment tester is used for testing a new product or a product of a mass production.
Manufacturers of the semiconductor device uses both the ATE and the application environment tester are used to carry out the test.
Because basic principles employed by the ATE and the application environment tester are different, it is difficult to embody the ATE and the application environment tester simultaneously. Moreover, the application environment tester cannot test multiple semiconductor devices simultaneously.
In case of the ATE, because the number of semiconductors that may be tested using the pattern generator 110 shown in FIG. 1 is limited, a plurality of the pattern generators 110 should be used to test the multiple semiconductor devices in the ATE.